EEL4712:  Digital Design, Fall 2012
Dept. of Electrical and Computer Engineering
University of Florida

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Syllabus

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Instructor:  Dr. Herman Lam

· Office Benton Hall, Room 313

· Office hours: M, T, W 1 – 2 pm, Th 11 am – 12 noon

· Telephone: (352) 392-2689 

· Email:  hlam@ufl.edu

TAs: TA Lab schedule and office hours (All office hours are in NEB 281, unless specified otherwise)

· Gautam Dash: gbdash@ufl.edu

o Office hour: W, Th 3 – 4 pm, F 4 – 5 pm (All TA office hours are in NEB 222)

· Sam Kerns: samkerns@ufl.edu

o Office hour: M, T 3 – 4 pm (All TA office hours are in NEB 222)

Class lectures:

· MWF 4th period (10:40 – 11:30 pm), Larsen Hall 330

Textbook:

· Brown, S. D. and Vranesic, Z. G., "Fundamentals of Digital Logic with VHDL Design", Latest Edition, McGraw-Hill

Altera DE0 Board:

· An FPGA-based laboratory board containing an Altera Cyclone III 3C16 FPGA device. Information on the DE0 Board can be found here, including the DE0 User Manual.

· The DE0 Board will be provided to you (included in your lab fee)

Design Software: Altera Quartus II Web Edition Software, latest version.

· Download Altera's Quartus installation file.

VHDL resources:

• Some examples and notes:

· Introduction to VHDL

· Some VHDL examples

· VHDL sequential statements Part A

· VHDL sequential statements Part B

· VHDL for state machines

· Another state machine example

· GenericVHDLExamples

• VHDL Quick Reference Card
• VHDL Tutorial: Learn by Example
• VHDL Online
• VHDL Reference

Grading:

· Test 1 (20%)

· Test 2 (25%)

· Labs (25%)

· Final Exam (30%)

There are no scheduled makeup tests. Makeup tests are handled case-by-case, only for documented illness and emergencies.

Course Objective:

        The objective of this course is to study the fundamentals, methodologies, and techniques for the structured design of digital systems, using the state of the art technologies and design environments and tools.

Course Contents:
I. Digital design building blocks and technologies

· Review of commonly-used digital components: MUXes, deMUXes, decoders, encoders, adders, flip-flops, counters, registers, etc.  In addition, we will learn to specify these components in VHDL.

· Carry-look-ahead adders, ALUs, multipliers

· Programmable logic devices: PAL's, PLA's, PROM's, CPLD's, and FPGA's

· Memories - RAM, dRAM, and ROM

II. Digital design methodology and techniques for finite state machines (FSM) and FGPA’s

· Top-down, modular design

· Controller/controlled-component architecture

· ASM fundamentals and design methods     

· Implementation methods - traditional, MUX, ROM, "one-hot"    

· Design and Implementation techniques using FPGA's 

· Testing and design for testing

· Digital design Examples (labs)

III. Design languages, tools, and environments (lab-intensive)

· Design life cycle using model digital development environments

· Design specification: graphical, VHDL

· Logic synthesis

· Simulation: functional and timing using VHDL testbenches

· Timing analysis

· Device program

· Testing

Academic honesty:

        Every assignment and exam is subject to the requirements stated in the Academic Honesty Student Guide . The items listed in the Academic Honesty Guidelines in that document will be strictly enforced. 

Accommodations for students with disabilities:

        Students requesting special classroom accommodation must first register with the Dean of Students Office.  The Dean of Students Office will provide documentation to the student who must then provide this documentation to the Instructor.