EEL4712:  Digital Design, Fall 2009
Dept. of Electrical and Computer Engineering
University of Florida

---

Syllabus

---

Instructor:  Dr. Herman Lam

· Office:  Larsen, Room 225

· Office hours: Mon 6^th period Tuesday 7^th period, Wed 4^th period, Thurs 5^th period, Fri 7^th period; I am also available other times; send me an email.

· Telephone: (352) 392-2689 

· Email:  hlam@ufl.edu

TAs: TA Lab schedule and office hours (All office hours are in NEB 281, unless specified otherwise)

· Carlo Pascoe: poppyc@ufl.edu

o Office hour: Monday 7^th period

· Robert G Kirchgerssner: rkirchge@gmail.com

o Office hour: Wednesday 6^th period and Wednesday 8^th period

Class lectures:

· MWF 5th period, NEB 202

Textbook:

· Brown, S. D. and Vranesic, Z. G., "Fundamentals of Digital Logic with VHDL Design", Second or Third Edition, McGraw-Hill

UF-4712 Board:

· An FPGA-based laboratory board containing an Altera Cyclone II EP2C8T144C8 FPGA. Information on the UF-4712 Board can be found in Dr. Schwartz’s Software/Docs page.

· The UF-4712 Board will be provided to you (included in your lab fee)

· A Byte Blaster is required, available at the UF Bookstore for $50 (if you don’t have one already).

Design Software: Altera Quartus II Web Edition Software, latest version.

· Download Altera's Quartus installation file.

References:

· VHDL Tutorial

· Dr. Schwartz’s Sofware/Docs page

Grading:

· Test 1 (20%)

· Test 2 (25%)

· Labs (25%)

· Final Exam (30%)

There are no scheduled makeup tests. Makeup tests are handled case-by-case, only for documented illness and emergencies.

Course Objective:

        The objective of this course is to study the fundamentals, methodologies, and techniques for the structured design of digital systems, using the state of the art technologies and design environments and tools.

Course Contents:
I. Digital design building blocks and technologies

· Review of commonly-used digital components: MUXes, deMUXes, decoders, encoders, adders, flip-flops, counters, registers, etc.  In addition, we will learn to specify these components in VHDL.

· Carry-look-ahead adders, ALUs, multipliers

· Programmable logic devices: PAL's, PLA's, PROM's, CPLD's, and FPGA's

· Memories - RAM, dRAM, and ROM

II. Digital design methodology and techniques for finite state machines (FSM) and FGPA’s

· Top-down, modular design

· Controller/controlled-component architecture

· ASM fundamentals and design methods     

· Implementation methods - traditional, MUX, ROM, "one-hot"    

· Design and Implementation techniques using FPGA's 

· Testing and design for testing

· Digital design Examples (labs)

III. Design environments and tools (lab-intensive)

· Design life cycle using model digital development environments

· Design specification: graphical, VHDL

· Logic synthesis

· Simulation: functional and timing

· Timing analysis

· Device program

· Testing

Academic honesty:

        Every assignment and exam is subject to the requirements stated in the  Academic Honesty Student Guide . The items listed in the Academic Honesty Guidelines in that document will be strictly enforced. 

Accommodations for students with disabilities:

        Students requesting special classroom accommodation must first register with the Dean of Students Office.  The Dean of Students Office will provide documentation to the student who must then provide this documentation to the Instructor.